Troy Meester
President and Founder - T&T Consulting
Principal Engineer - ASIC Design
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With 25 years of experience in Electrical Engineering and the Semiconductor Industry I have gained a conserderable number of skills. Solving engineering problems under a variety of contraints and conditions has provided me with an challenging and rewarding career.
Many of my empolyers have been small companies with limited capital resources. Yet, I have been able to assist them in putting successful products on the market.
I'm always looking for companies looking to develop new technology ideas into successful product lines.
Let's talk about your product development issues and how T & T Consulting can put together an experienced team to bring you success. |
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Robert Hoffman
Engineering Design Manager - ASIC Design
Resume: ( .doc | .pdf ) |
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My background in Electrical Engineering and over 25 years experience in the semiconductor industry has provided me wealth of knowledge in chip design and project management. I've been fortunate enough to work on a variety of projects in different areas such as Non-Volatile Memories, Wireless Networking, Cryptography, RFID, Image Compression and numerous other projects. My involvement in these projects spans the range from Verilog RTL development, design verification, architecture development to project management.
Please contact T & T Consulting and we'll make your project a success story. |
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Christopher L. Smith
Staff Design Engineer - ASIC Design
Resume: ( .doc | .pdf ) |
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Experienced Circuit Design Engineer and Technical Leader with significant background in design, test, and validation of Integrated Circuits. Extensive experience and qualifications in all facets of the product life cycle, from initial feasibility analysis and conceptual design through documentation, design, validation, and characterization. |
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Brad Meacham
Senior Staff Engineer - ASIC Design
Resume: ( .doc | .pdf ) |
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ECAD engineer with over 20 years EDA experience using the Verilog language at gate, RTL, and behavioral level as wellas the Verilog PLI and VPI extensions and logic design verification with the Verilog HDL and C/C++ based co–simulation |
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Tim E. Fiscus
Program Manager/Senior Staff Engineer - ASIC Design
Resume: ( .doc | .pdf ) |
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Experienced program manager, technical leader, and designer with proven success in development for small and large organizations worldwide. |
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